MC56F8002VWL

Product Summary

The MC56F8002VWL is a member of the 56800E core-based family of digital signal controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create a cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the MC56F8002VWL is well-suited for many applications. The MC56F8002VWL includes many peripherals that are especially useful for cost-sensitive applications, including: Industrial control, Home appliances, Smart sensors, Fire and security systems, Switched-mode power supply and power management, Power metering, Motor control (ACIM, BLDC, PMSM, SR, and stepper), Handheld power tools.

Parametrics

MC56F8002VWL absolute maximum ratings: (1)Supply Voltage Range:-0.3V to 3.8V; (2)Analog Supply Voltage Range:- 0.3V to 3.6V; (3)Voltage difference VDD to VDDA:- 0.3V to 0.3V; (4)Voltage difference VSS to VSSA:- 0.3V to 0.3V; (5)Digital Input Voltage Range(Pin Groups 1, 2): - 0.3V to VDD+0.3V; (6)Oscillator Voltage Range(Pin Group 4): TBD to TBD V; (7)Analog Input Voltage Range(Pin Group 3): - 0.3V to 3.6V; (8)Input clamp current, per pin (VIN < 0)1:-25 mA; (9)Output clamp current, per pin (VO < 0)1:-20.0 mA; (10)Output Voltage Range (Normal Push-Pull mode)(Pin Group 1): -0.3V to VDD V; (11)Ambient Temperature Industrial:- 40℃ to 105℃; (12)Storage Temperature Range (Extended Industrial):-55℃ to 150℃.

Features

MC56F8002VWL features: (1)Up to 32 MIPS at 32 MHz core frequency; (2)DSP and MCU functionality in a unified, C-efficient architecture; (3)One 6-channel PWM module; (4)Two 28-channel, 12-bit analog-to-digital converters (ADCs); (5)Two programmable gain amplifiers (PGA) with gain up to 32x; (6)Three analog comparators; (7)One programmable interval timer (PIT); (8)One high-speed serial communication interface (SCI) with LIN slave functionality; (9)One serial peripheral interface (SPI); (10)One 16-bit dual timer (2 x 16 bit timers); (11)One programmable delay block (PDB).

Diagrams